Why Your Real-Time System Misses Deadlines
An IRQ Latency Deep Dive: Method and Architecture
Introduction
Real-time systems don't fail loudly, they fail silently.
A missed deadline in an embedded system rarely throws an exception. Instead, it manifests as unstable control loops, inconsistent sensor fusion, delayed actuation, or worst, non-reproducible field failures.
In most cases the root cause is not "slow code", it is interrupt latency and jitter.
What \"Missing Deadlines\" Really Means
A real-time system is not about speed, it is about predictability. Even with a low average latency a system fails if the worst case exceeds its timing constraint, if jitter becomes unpredictable, or if interrupts cannot preempt critical paths.
Root Cause: IRQ Latency
IRQ latency is the time between the interrupt trigger and the start of ISR execution. It is not constant: interrupt priority configuration, the current execution context, memory and cache state, bus contention and ISR nesting all move it.
Where It Grows
- NVIC priority misconfiguration. Incorrect priority grouping prevents critical interrupts from preempting lower-priority work.
- An ISR doing too much. Heavy ISR logic blocks other interrupts and cascades latency across the system.
- Memory and cache effects. Cache misses and memory contention introduce unpredictable delays.
- Interrupt storms. Several sources competing for CPU time make scheduling non-deterministic.
- Hidden RTOS interactions. Scheduler decisions interfere with interrupt handling under load.
How to Measure It (The Right Way)
Wrong: software timestamps, logging-based measurement.
Correct: a GPIO toggle inside the ISR, read with external equipment (oscilloscope or logic analyser), repeated under sustained load, with the worst case reported alongside the average.
What Changes the Answer
Moving non-critical work out of the ISR, deferring heavy logic, restructuring the NVIC priority hierarchy, relocating critical data to reduce cache misses, and switching to a direct interrupt dispatch mechanism so the RTOS leaves the critical path.
Engineering Note
Low average latency is meaningless without a low worst case. Determinism is not about speed, it is about guarantees.
A number without its setup is not evidence. When we publish one, the bench and the method are published with it.